1. Field of the Invention
The present invention relates to techniques for supporting design of semiconductor circuits such as LSIs by using computers, and in particular relates to techniques for supporting design of circuits including timing exception paths.
2. Description of the Related Art
In recent years, semiconductor circuits have generally been designed using RTL (Register Transfer Level) descriptions, and logic synthesis tools for performing logic synthesis of circuit data in RTL descriptions to automatically generate gate-level circuits have been utilized (see, for example, JP-A-2003-216672).
For example, an existing logic synthesis tool performs logic synthesis on the basis of the following arithmetic expression:Expression: Z=A×B×C 
In this case, logic synthesis is performed using the following different timing constraints 1 and 2.
Constraint 1: A, B and C are all “true path”
Constraint 2: A and C are “false path (timing exception)” but B is “true path”
With the existing logic synthesis tool, results of the logic synthesis, performed using Constraints 1 and 2, both have a structure illustrated in FIG. 4 described later, and thus identical logic circuits are generated.
In other words, when logic synthesis is performed on the basis of the above-described computing equation, there is a problem in that the existing logic synthesis tool is incapable of generating a logic circuit in consideration of a timing exception set by a timing constraint.